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Contemporary electronic systems have to provide high performance and, also, be energy-efficient and robust. Until recently, tolerance against a given set of single faults was sufficient to have a system operating reliably. Nowadays, in the face of high system complexity and significant parameter variations, a high level of robustness is required to guarantee reliable operation. The system must be prepared to withstand a large class of partially unanticipated fault effects and adverse operating conditions. When devising measures for increasing the robustness, the power and silicon area overhead must be carefully minimized.

Asynchronous design methods are generally considered very robust. This robustness can be witnessed mainly in the timing domain, where PVT changes are easily accommodated without malfunction, i.e., the self-adaptivity of asynchronous design enables operation at the pace provided by the actual process, voltage, and temperature (PVT) parameters. To enhance the use of asynchronous logic, it is, however, necessary to ensure the robustness of this approach to the different fault sources as well. It is required to deeply understand and leverage the potential benefits of asynchronous design methods. Soft errors, such as single-event transients and single-event upsets, are very critical for avionic and space applications. With technology scaling, the critical charge of transistors is reduced, and the soft error rate (SER) increases dramatically, causing the need for fault mitigation in the terrestrial use of the technology. Nowadays, the concern is not only about single events but there is a need to mitigate multi-bit errors. At the same time, even fault-tolerant circuits and applications urge for power reduction and require aggressive voltage scaling, which makes the use of asynchronous logic very attractive. In this setting, timing errors and upsets/transients must be dealt with, but there is no satisfactory solution in the standard synchronous domain.

Considering that the requirements for timing flexibility are growing, while at the same time, the synchronous approach is not naturally suited to fulfill them, makes the asynchronous paradigm is the focus of the ENROL project. ENROL project goal is to ensure robustness in efficient asynchronous circuits, systematically classifying and extending transient-fault mitigation techniques (on circuit and architecture level) with a broad coverage. From the bottom-up, starting with a comprehensive fault modeling, up to a quantitative experimental assessment of their respective effectiveness, thus allowing comparisons and further optimization. Moreover, ENROL goes beyond today's simplified and unrealistic limits of single-event transients. Multi-bit errors resulting from a single transient event are addressed in ENROL both at the physical, i.e., spatial, and architectural levels.