library IEEE; use IEEE.STD_LOGIC_1164.ALL; use IEEE.STD_LOGIC_ARITH.ALL; use IEEE.STD_LOGIC_UNSIGNED.ALL; entity alu is generic ( WD : integer := 16 ); port ( a, b : in std_logic_vector(WD-1 downto 0); s : in std_logic_vector(1 downto 0); o : out std_logic_vector(WD-1 downto 0)); end alu; architecture Behavioral of alu is begin process (a,b,s) begin if (s = "10") then o <= a+b; elsif (s = "01") then o <= a-b; elsif (s = "11") then o <= not a; end if; end process; process (o) begin if (clk'event and clk = '1') then s <= o; end if; end process; end Behavioral;